Non-volatile memories require a column multiplexer that can pass read bias voltages onto the bitlines for generating read currents through the memory cell. The column multiplexer is also required to withstand high voltages because the bitlines get high voltage biases during program/erase non-volatile operations. In state of the art technologies, the power supply is also very low (typically less than 1.8v). Since the pass device of the column multiplexer device has to withstand high voltages (around 10V), they have to be thick oxide devices which have high threshold voltages. Due to the high threshold voltages of the high voltage devices and limited power supply headroom, column multiplexers have difficulty passing the read bias voltage onto the bitlines to generate sufficient read currents. As a result, the speed across the column multiplexer is degraded due to high voltage devices and power supply headroom issues. This is even more critical for large density memories where the bitline resistance and capacitances are high causing speed pushouts. In addition, these thick oxide devices require a large area to increase the read currents, which takes up valuable chip area.
Thus, there exists a need for column multiplexer circuit that has good speed during read operations and has a small footprint.